1. Field
The present invention concerns a frequency synthesis device with feedback loop.
2. Description of the Related Art
Such devices are known, for example controlled phase loops known as PLLs, generally referred to as phase locked loops, or delay locked loops (DLLs).
These devices can commonly be represented schematically by a device such as the one in FIG. 1, comprising a phase comparison control circuit 10, a frequency conversion unit 12 voltage controlled by the control circuit 10 and a feedback loop 14 for supplying a signal issuing from the frequency conversion unit 12 to the control circuit 10.
More precisely, in the case of PLLs and DLLs, the control circuit 10 comprises a phase comparator 16 with two outputs (generally called UP and DOWN), receiving as an input a reference signal at a frequency Fin supplied by a reference frequency source 18 and the signal issuing from the frequency conversion unit 12 supplied by the feedback loop 14. It further comprises a charge pump 20 that injects or removes charges in or from a filtering or smoothing device 22 by means of two current sources controlled by the UP and DOWN outputs of the phase comparator 16. This enables the control circuit to supply a voltage at the output of the filtering or smoothing device 22 that is determined, for example proportionally, by the comparison of the signal supplied by the feedback loop with the reference signal.
For a PLL, the device 22 is more particularly a filter and the frequency conversion unit 12 comprises an internal oscillator controlled by voltage, the one supplied by the control circuit 10, for supplying an output signal at a frequency Fout that is a multiple of the frequency Fin and a divider for obtaining, from the output signal, a signal at the frequency Fin to be supplied to the feedback loop 14. The voltage control makes it possible to finely regulate the frequency of the internal oscillator.
For a DLL, the device 22 is more particularly a smoothing capacitor unit and the frequency conversion unit 12 comprises a delay line controlled by voltage, the one supplied by the control circuit 10, for generating P out-of-phase signals at the frequency Fin from the signal supplied by the reference frequency source 18 via a connection 24, and a frequency multiplier receiving these P out-of-phase signals for supplying an output signal at a frequency Fout that is a multiple of the frequency Fin, more precisely at the frequency Fout=P/2Fin. The signal supplied to the phase comparator 16 by the feedback loop 14 is one of the P out-of-phase signals supplied by the voltage-control delay line, for example the first. The control voltage makes it possible to finely regulate the phase shifting of the P signals generated by the delay line.
The PLLs and DLLs are thus generally used in electronic circuits as high frequency sources. This is because these devices make it possible, from a low-frequency and high spectral purity source (for example quartz crystal emitting at a few MHz), to obtain high-frequency signals (for example a few GHz) with a spectral purity of better quality than the devices directly generating high-frequency signals.
In concrete terms, for a source with a low reference frequency and a high spectral purity Fin, a signal of good spectral purity at high frequency Fout=NFin, N being a multiplying factor, is obtained at the output. This multiplying factor N is generally variable so as to vary the various channels of the standards used according to the application.
An important parameter of frequency synthesis devices is the time Δt for establishing their operating regime, that is to say the time that they take to be functional, either at start-up, or when there is a change of channel (i.e. change in the factor N). This time Δt endures during a transient regime, generally termed an engagement phase, preceding the operating regime.
An example of transient regime followed by a frequency synthesis device when there is a change of channel is illustrated in FIG. 2. When there is a change ΔFout from a frequency Fout to a frequency F′out, the transient synthesised frequency regime follows an exponential envelope tending asymptotically towards F′out at a natural resonant frequency ωn during the period Δt.
The period Δt of the engagement phase depends on the parameters constituting the frequency synthesis device and limits the reactivity thereof.
The patent application published under the number US 2002/0043995 describes a phase comparator, the internal structure of which reduces the duration of the engagement phase of the PLL or DLL device in which it is used. By virtue of this phase comparator, the frequency of the reference source is rapidly in phase with the output of the divider (in the case of the DLL) or the voltage-controlled delay line (in the case of the PLL). However, this reduction in the duration of the engagement phase is obtained at the cost of a greatly increased complexity of the phase comparator.
The patent application published under the number US 2007/0285132 describes a PLL comprising a selective charge pump connected to two phase comparators for accelerating the establishment of the operating regime. However, there also, this result is obtained at the cost of a complexity of the elements connecting the two phase comparators to the selective charge pump.
It may thus be desired to provide a frequency synthesis device with feedback loop that has a time for establishing its operating regime that is as short as possible while dispensing with at least some of the aforementioned problems and constraints.